The present invention relates to a semiconductor memory device; and, more particularly, to prefetch a 4-bit data at once and effectively arrange the prefetched data in pipelining latches.
In a conventional semiconductor memory device, two data are prefetched at once. Namely, each of the two data are simultaneously prefetched through different paths by one instruction for reading data stored in the cells of the semiconductor memory device. The two data can be inputted in serial or parallel. The two latched data is outputted according to a rising and a falling edge of a clock signal.
Today, the semiconductor memory device should be operated on higher speed. Typically, a frequency of the clock signal is increased for fast operation of the semiconductor memory device, but there is a limit to using the above mentioned method for prefetching data. Thus, it is needed to access and prefetch more bit data at once.
In addition, the read data prefetched at once should be used effectively. If it takes a long time to arrange a lot of data which are prefetched at once, the delay time is increased and, as a result, the semiconductor memory device can rather operate slowly. For example, although more pipelining latches are used for prefetching data, an address access time tAA is increased, if a lot of the prefetched data should be arranged in the pipelining latches. It is because the address access time tAA includes a latching time for latching the prefetched data in pipelining latches and outputting to an output driver.
It is, therefore, an object of the present invention to provide a semiconductor memory device having an advanced prefetching block for prefetching multiple bits of data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device.
In accordance with an aspect of the present invention, there is provided the semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals including a first data multiplexing unit for receiving a first even datum from a first even line and a first odd datum from a first odd line and determining a data path of each of the first even and odd data between first and second data paths according to a data assigning control signal and outputting a first datum through the first data path and outputting a second datum through the second data path; a second data multiplexing unit for receiving a second even datum from a second even line and a second odd datum from a second odd line and determining a data path of each of the second even and odd data between third and forth data paths according to the data assigning control signal and outputting a third datum through the third data path and outputting a forth datum through the forth data path; a third order multiplexing unit for receiving the first datum from the first data path and the third datum from the third data path and sequentially outputting the first and the third data at a rising edge of a first control signal in response to the start address of the inputted data; and a forth order multiplexing unit for receiving the second datum from the second data path and the forth datum from the forth data path and sequentially outputting the second and forth data to a falling edge of a second control signal in response to the start address of the inputted data, wherein the 4-bit data is split into the first even data, the first odd data, the second even data and the second odd data, and the data assigning control signal is used for arranging a inputted data into a data path according to whether the start address of the inputted data is an even number or an odd number.
In accordance with an aspect of the present invention, there is provided the semiconductor memory device for prefetching 4-bit data from at least one bank in response to an instruction for reading data including a first control signal generating unit for generating a first and a second control signals generated by logically combining a data input control signal with a data output control signal; a second control signal generating unit for generating a third control signal and a forth control signal, the third control signal generated by logically combining a odd enable signal which is used for outputting an odd times data with a odd arranging signal which is used for arranging the odd times data in response to a start address of the 4-bit data, the forth controls signal generated by logically combining a even enable signal which is used for outputting an even times data with a even arranging signal which is used for arranging the even times data in response to a start address of the 4-bit data; and a signal delivering unit controlled by the first, the second and the third control signals for outputting the 4-bit data to a first and a second even data output lines and a first and a second odd data output lines.